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Nr cleanup#98

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akashlevy merged 26 commits intomainfrom
nr_cleanup
Feb 4, 2026
Merged

Nr cleanup#98
akashlevy merged 26 commits intomainfrom
nr_cleanup

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@AdvaySingh1
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@AdvaySingh1 AdvaySingh1 commented Jan 30, 2026

Node retention PR.

Changed blifparse, abc.cc, and abc submodule.


Important

Adds node retention parsing and propagation in Yosys synthesis tool to track and annotate signal source origins.

  • Behavior:
    • Adds parsing for .node_retention_begin and .node_retention_end sections in parse_blif() in blifparse.cc to track signal source origins.
    • Updates prepare_module() in abc.cc to include node retention options in the ABC script.
    • Modifies extract() in abc.cc to propagate node retention sources to wire attributes.
  • Configuration:
    • Introduces abc_node_retention and abc_max_node_retention_origins options in AbcConfig in abc.cc to control node retention behavior.
  • Misc:
    • Updates ABC submodule to commit 82fdc5a81df8dcdd798eea56ecdc9f5a24f32813.

This description was created by Ellipsis for 8d22f6d. You can customize this summary. It will automatically update as commits are pushed.

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Looks good to me! 👍

Reviewed everything up to 7dab62c in 27 seconds. Click for details.
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greptile-apps bot commented Jan 30, 2026

Greptile Overview

Greptile Summary

This PR implements node retention functionality to track and propagate signal source origins through the ABC optimization flow.

Changes:

  • Added parsing of .node_retention_begin/.node_retention_end blocks in BLIF files (blifparse.cc) with clear explanatory comments per custom instructions
  • Extended AbcConfig with abc_node_retention flag and conditionally adds -r flag to ABC's read_blif command
  • Modified ABC result re-integration to propagate \node_retention_sources attributes to wire and cell src attributes using string pools
  • Updated ABC submodule to support the -r flag

Issues:

  • Critical: Missing design->select(module, cell); call at abc.cc:1755 - generic cells won't be properly selected
  • Minor: Incomplete warning message at abc.cc:1483 missing source node identifier

Confidence Score: 2/5

  • This PR has a critical logic bug that must be fixed before merging
  • The missing design->select(module, cell); call at line 1755 in abc.cc is a critical bug that will cause generic cells to not be properly added to the design selection, potentially breaking the ABC integration for certain cell types. All other cell types in the same function correctly call design->select() after creation.
  • passes/techmap/abc.cc requires immediate attention to fix missing design->select() call

Important Files Changed

Filename Overview
frontends/blif/blifparse.cc Added node retention parsing with good comments per custom instructions; control flow with read_next_line() handles EOF correctly
passes/techmap/abc.cc Node retention source tracking added; critical bug - missing design->select() call for generic cell type (line 1755); warning message incomplete

Sequence Diagram

sequenceDiagram
    participant User
    participant Yosys
    participant BlifParser as blifparse.cc
    participant AbcPass as abc.cc
    participant ABC as ABC Tool
    
    User->>Yosys: Set abc.node_retention flag
    User->>Yosys: Run ABC pass
    
    Note over Yosys,ABC: Export Phase
    Yosys->>AbcPass: prepare_module()
    AbcPass->>AbcPass: Check abc_node_retention flag
    alt node_retention enabled
        AbcPass->>AbcPass: Add "-r" to read_blif command
    end
    AbcPass->>ABC: Export to input.blif
    AbcPass->>ABC: run read_blif [-r] "input.blif"
    ABC->>ABC: Process with node retention
    ABC->>AbcPass: Write output.blif with node retention data
    
    Note over Yosys,ABC: Import Phase
    AbcPass->>BlifParser: parse_blif(output.blif)
    BlifParser->>BlifParser: Parse .node_retention_begin block
    loop for each node_name SRC sources
        BlifParser->>BlifParser: Find wire by node_name
        BlifParser->>BlifParser: Set \node_retention_sources attribute
    end
    BlifParser->>BlifParser: Parse .node_retention_end
    BlifParser->>AbcPass: Return parsed design
    
    Note over Yosys,ABC: Re-integration Phase
    AbcPass->>AbcPass: extract() - re-integrate ABC results
    loop for each wire with \node_retention_sources
        AbcPass->>AbcPass: Parse sources string
        loop for each source node
            AbcPass->>AbcPass: remap_name(source, &orig_wire)
            AbcPass->>AbcPass: Add orig_wire src to pool
        end
        AbcPass->>AbcPass: wire->add_strpool_attribute(src, pool)
    end
    loop for each cell
        AbcPass->>AbcPass: Get output wire's src pool
        AbcPass->>AbcPass: cell->add_strpool_attribute(src, pool)
        AbcPass->>Yosys: design->select(module, cell)
    end
    
    AbcPass->>Yosys: Return optimized module
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3 files reviewed, 7 comments

Edit Code Review Agent Settings | Greptile

Wire *out_wire = c->getPort((c->hasPort(ID::Y)) ? ID::Y : ID::Q).as_wire();
Wire *remapped_out_wire = module->wire(remap_name(out_wire->name));
std::string src_attribute = sig2src[remapped_out_wire];
log("Processing cell %s\n", c->name.c_str());
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this debug log will print for every cell in mapped design - can create excessive output. Consider using log_debug() or removing

Prompt To Fix With AI
This is a comment left during a code review.
Path: passes/techmap/abc.cc
Line: 1493:1493

Comment:
this debug log will print for every cell in mapped design - can create excessive output. Consider using `log_debug()` or removing

How can I resolve this? If you propose a fix, please make it concise.

}
wire->add_strpool_attribute(ID::src, src_pool);
} else {
log("No node retention sources found for wire %s\n", w->name.c_str());
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this log will print for every wire without node retention sources - likely excessive output. Consider using log_debug() or only logging when expected

Note: If this suggestion doesn't match your team's coding style, reply to this and let me know. I'll remember it for next time!

Prompt To Fix With AI
This is a comment left during a code review.
Path: passes/techmap/abc.cc
Line: 1480:1480

Comment:
this log will print for every wire without node retention sources - likely excessive output. Consider using `log_debug()` or only logging when expected

<sub>Note: If this suggestion doesn't match your team's coding style, reply to this and let me know. I'll remember it for next time!</sub>

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Should this ever happen? If not, this should be a warning not INFO. If it happens a lot, it should be debug

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Based on the context, this should be log_debug().

Node retention sources are only present on specific wires that have node retention information from .node_retention_begin/.node_retention_end blocks in BLIF files. In a typical design, most wires won't have this specialized attribute, so the current INFO log would fire for the majority of wires, creating excessive noise.

Suggested change
log("No node retention sources found for wire %s\n", w->name.c_str());
} else {
log_debug("No node retention sources found for wire %s\n", w->name.c_str());

This keeps the information available for debugging while avoiding cluttering the output during normal operation.

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greptile-apps bot commented Jan 30, 2026

Additional Comments (1)

passes/techmap/abc.cc
removed error handling for ABC script failures - if ABC prints an error and returns to prompt, this will now hang waiting for YOSYS_ABC_DONE instead of failing gracefully. Was this removal intentional?

Prompt To Fix With AI
This is a comment left during a code review.
Path: passes/techmap/abc.cc
Line: 1150:1157

Comment:
removed error handling for ABC script failures - if ABC prints an error and returns to prompt, this will now hang waiting for `YOSYS_ABC_DONE` instead of failing gracefully. Was this removal intentional?

How can I resolve this? If you propose a fix, please make it concise.

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}
wire->add_strpool_attribute(ID::src, src_pool);
} else {
log("No node retention sources found for wire %s\n", w->name.c_str());

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Should this ever happen? If not, this should be a warning not INFO. If it happens a lot, it should be debug

@akashlevy
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I think your blifparse removal is causing the tests to fail... please double check

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@greptile please review

blif_maxnum = 0;
}

// Parse optional node retention section that tracks signal source origins for ABC reintegration.

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Can you indent this to be consistent with everything surrounding?

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2 files reviewed, 2 comments

Edit Code Review Agent Settings | Greptile

AdvaySingh1 and others added 4 commits February 3, 2026 08:33
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
…case cells

Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
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Will update the abc submodule when that PR is 100% ready

@akashlevy akashlevy self-assigned this Feb 4, 2026
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@akashlevy akashlevy merged commit dbeeb7a into main Feb 4, 2026
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